It is well known in the art that polysilicon may be used as gate electrode in semiconductor devices such as, for example, field-effect-transistors (FETs) and in particular complementary metal-oxide-semiconductor field-effect-transistors (CMOS-FETs). On the other hand, with the continuing scaling down in dimensions of semiconductor devices, other types of gate electrodes such as, for example, metal and/or fully silicided (FUSI) gate electrodes are being used to replace the conventional polysilicon gate electrodes. Metal and/or FUSI gate electrodes may reduce and/or prevent depletion of charges, commonly known as poly-depletion, associated with polysilicon gate electrode. Occurring in the vicinity of an interface between a polysilicon gate electrode and a gate dielectric, poly-depletion may lead to less induced charges in the channel region of a FET device causing lower current and degraded performance. Compared with using polysilicon gate electrodes, the use of metal and/or FUSI gate electrodes may reduce an effective thickness of the gate dielectric, and thus increase the capacitance associated with the gate, or gate capacitance. The increase in gate capacitance effectively increases the amount of induced charges in the channel region of the FET device, which translates to higher drive currents and transistor performance.
On the other hand, there are situations where it may be difficult to use metal gate electrodes in certain device areas having devices with multiple threshold voltages. Metal gate and/or FUSI gate electrodes tend to have workfunctions near the mid-gap of silicon. Workfunctions near the mid-gap of silicon lead to higher than desirable threshold voltages. The standard way to reduce threshold voltage is to decrease the channel doping of the device; however, this leads to degraded short channel control. The net result is that metal gate electrodes with workfunctions near the mid-gap of silicon do not have a device design point for FETs with a low threshold voltage.
It is also known in the art that when FUSI is performed on a highly doped n+ polysilicon of a FET gate (nFET), the resultant FUSI gate electrode may have a workfunction value that is operational. However, performing FUSI on a FET gate with highly doped p+ polysilicon (pFET) may not necessarily create a workfunction value that is compatible or desirable for the intended devices.
For instance, with some state of the art FET devices, the magnitude of threshold voltages with highly doped n+ polysilicon electrodes may range from, for example, 0.15V-0.55 V depending upon the type of technology used. A threshold voltage is known to determine when a CMOS-FET turns on and/or off. Lower magnitudes of threshold voltage may create a FET with higher current and high power consumption while higher magnitudes of threshold voltage may result in a FET with lower current and lower power consumption. For example, magnitude of threshold voltage for a high performance device may be as low as 0.15V while for low power devices the threshold voltage may be as high as 0.55V. In general, multiple-threshold voltages are needed in semiconductor technology to provide flexibility in design for low-power, high-performance, and mixed-signal applications.
Applying FUSI using known methods may increase the magnitude of threshold voltage by around 250 mV to 500 mV due to changes in the workfunction of the gate electrode. This increase in threshold is often not desirable for FET devices that require low magnitudes of threshold voltage to achieve high performance. It is possible to apply FUSI to a FET device while maintaining a desired magnitude of threshold voltage by, for example, decreasing a doping concentration in a channel region of the substrate. This is because decreasing the channel doping may decrease the magnitude of the threshold voltage, countering the increase due to the application of FUSI. Nevertheless, decreasing the channel doping to a critical level may create a FET that does not function properly. If the substrate doping is too low then the source/drain regions may form a short circuit that may no longer be controllable by the gate electrode. This could lead to a FET that cannot be turned off and thus becomes useless. Specifically, FETs with already low magnitudes of threshold voltages (0.15V-0.25V) are not compatible with current state of the art FUSI. Using FUSI gate electrodes on these devices would result in FETs that cannot be turned off due to the reduction of substrate doping required in order to achieve the desired low magnitude of threshold voltage. However, FETs that have threshold voltages in the 0.3V-0.55V range are compatible with FUSI gate electrodes because the substrate doping is relatively high for these FETs when polysilicon gate electrodes are used. Using FUSI gate electrodes on FETs with threshold voltages in the range of 0.3V-0.55V may be achieved by decreasing the substrate doping to account for the 250 mV-500 mV increase caused by the change in FUSI gate electrode workfunction.
It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity.